The testing and failure analysis of integrated semiconductor devices is well known and a number of Failure Analysis (FA) tools have been developed. For example it is known from U.S. Pat. No. 5,760,892 to provide a method of analyzing failure of a semiconductor device using an emission microscope.
It is also known from U.S. Pat. No. 6,153,891 to provide a method and apparatus providing a circuit edit structure through the backside of an integrated circuit die.
It is also known from U.S. Pat. No. 5,294,812 to provide a semiconductor device having an identification region which may be inspected by eye in order to discern information about the device.
Typically, such FA tools are used to measure and evaluate the performance of an integrated circuit are specified by physical signal parameters such as rise time, timing/jitter measurements, spatial visible resolution between diffusion/metals and crosstalk between adjacent phase-shifted signals. These parameters are measured and used to define performance criteria for the integrated circuit.
A known problem with such arrangements is that the abovementioned physical parameters are not readily isolated and identified from within the integrated circuitry. Particularly in the field of new and emerging process technologies and materials, calculations and derivations of the performance criteria must be made during the analysis itself, often in an iterative way, leading to a lengthy and complex procedure.
A need therefore exists for an analysis module, integrated circuit, system and method for testing an integrated circuit wherein the abovementioned disadvantage (s) may be alleviated.